/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/**
 * @file  SpiSlave_Irq.c
 * @brief Semidrive. AUTOSAR 4.3.1 MCAL SpiSlave_Slave plugins.
 */
#ifdef __cplusplus
extern "C" {
#endif

#include "RegHelper.h"
#include "regs_base.h"
#include "SpiSlave.h"
#include "SpiSlave_Ip.h"
#include "SpiSlave_Mld.h"
#include "SpiSlave_reg.h"
#include "SpiSlave_Driver.h"

#define SPI_SLV_START_SEC_CODE_FAST
#include "SpiSlave_MemMap.h"

#if ( SPI_SLV_LEVEL_DELIVERED == SPI_SLV_LEVEL_1) || ( SPI_SLV_LEVEL_DELIVERED == SPI_SLV_LEVEL_2)
/** @brief SpiSlave_ChannelDetCheck
 **
 ** To perform basic DET checks related to channels
 **
 ** @param [in] Channel   - Channel ID.
 ** @param [in] SId  - Service ID for Error Reporting
 ** @param [out] None
 ** @return  E_OK: No err related to channels be detected.
 **          E_NOT_OK: The err related to channels be detected.
 */
static FUNC(void, SPI_SLV_CODE)
spi_slv_intr_hdlr(struct mld_spi_slv_module * spi)
{
    struct SpiSlave_Driver_Handler *PerCoreHandler = SpiSlaveHandler[SpiSlave_GetCoreID()];
    struct SpiSlave_Scheduler *Sche = &PerCoreHandler->Scheduler;

    if (Sche->SchedulerMode == SPI_SLV_INTERRUPT_MODE) {
        SpiSlave_HwMainFunctionHandling(spi->idx);
    }
}
/** @brief SpiSlave1 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave1_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB1].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI1_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave2 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave2_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB2].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI2_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave3 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave3_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB3].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI3_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave4 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave4_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB4].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI4_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave5 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave5_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB5].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI5_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave6 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave6_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB6].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI6_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave7 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave7_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB7].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI7_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave8 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave8_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB8].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI8_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave3 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave9_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB9].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI9_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave4 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave10_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB10].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI10_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave5 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave11_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB11].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI11_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave6 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave12_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB12].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI12_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave7 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave13_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB13].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI13_BASE + SPI_IRQ_MASK_OFF);
    }
}
/** @brief SpiSlave8 Irq Handler
 **
 ** To Handler the SpiSlave tramission events
 **
 ** @param [in] None
 ** @param [out] None
 ** @return  None
 */
void SpiSlave14_IrqHandler(void)
{
    struct mld_spi_slv_module *SpiSlave_Slave = &SpiSlaveHandler[SpiSlave_GetCoreID()]->SpiBus[SPI_SLV_CSIB14].Bus;
    spi_slv_intr_hdlr(SpiSlave_Slave);

    if (0u == (SpiSlave_Slave->state & SPI_SLV_STATE_INITED)) {
        /*  Unexpected interrupt, mask all interrupts */
        writel(0xFFFFFFFF, APB_SPI14_BASE + SPI_IRQ_MASK_OFF);
    }
}
#endif

#define SPI_SLV_STOP_SEC_CODE_FAST
#include "SpiSlave_MemMap.h"

#ifdef __cplusplus
}
#endif
